1. Field of the Invention
The present invention relates to a method used to fabricate high density, semiconductor, DRAM cells, with stacked capacitor structures, and more specifically to a fabrication process used to increase the surface area of a storage node electrode, used in the stacked capacitor structure.
2. Description of the Prior Art
Device performance and cost reductions are the major objectives of the semiconductor industry. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of a source/drain of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 256 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
Two methods that can be used to increase STC capacitance, while still decreasing the lateral dimension of the capacitor, are the use of rough, or hemispherical grain (HSG), silicon layers, and the use of crown shaped STC structures. First, referring to the crown shaped STC structures, the creation of a polysilicon, or amorphous silicon, storage node electrode structure, comprised of both vertical and horizontal silicon features, results in a greater electrode surface area then would have been achieved with counterparts fabricated without vertical features. Secondly the use of an HSG silicon layer, comprised of convex and concave features, and used for the top layer of the storage node electrode structure, again results in a greater degree of surface area then counterparts fabricated with smooth silicon layers. Therefore the combination of a crown shaped STC structure, comprised with a top layer of HSG silicon, residing on the crown shaped storage node structure, is an attractive option for high density DRAM devices. However if a HSG silicon layer is used with a crown shaped storage node electrode, the space between the vertical features, of the crown shaped structure, has to be increased to accept the growth of the HSG silicon layer, on the inside walls of the vertical features. If this space were kept at a minimum, HSG silicon, residing on neighboring inside walls of the vertical features, may intersect, leaving little, or no space remaining for the capacitor dielectric layer, thus negating the advantage of increased surface area using the combination of HSG silicon and the crown shaped structures. If the space between vertical features, of the crown shaped structure, were increased to accept the additional growth of the HSG silicon layer, on the inside walls of the crown shaped storage node electrode, the final dimension of the DRAM capacitor structure may violate design groundrules.
This invention will describe a novel process for the fabrication of a crown shaped STC structure, however incorporating a selective growth of an HSG silicon layer, to occur only on the outside walls of the vertical features of the crown shaped STC structure. The selective growth of the HSG silicon layer, only on the outside walls of the vertical features, of the crown shaped STC, thus allows the minimum space between vertical features to still be maintained, and thus also allows a minimum lateral dimension for the DRAM capacitor structure, to be achieved. Prior art, such as Tseng, in U.S. Pat. No. 5,716,883, describes a fabrication method for a crown shaped STC structure, while Lou, et al, in U.S. Pat. No. 5,597,754, describe a method for forming an HSG silicon layer, for a DRAM storage node structure. However none of the prior art describe the process used in the present invention, in which selective growth of an HSG silicon layer, is achieved only on the outside walls. of vertical features, of a crown shaped STC structure.